1. Field of the Invention
The present invention relates to a method for etching an upper metal of a capacitor, and more particularly, to a method for forming an upper metal layer of a capacitor by over etching more than 50% in combination with using CHF3, Ar, and N2.
2. Discussion of the Related Art
Recently, as a degree of device integration becomes higher, a cell area allocated for reading and recording an electric signal is gradually reduced.
For example, in a case of 256 Mb DRAM, the cell area is 0.5 μm2. In this case, an area allocated to a capacitor, as one of basic elements of the cell, should be less than 0.3 μm 2.
According to such an improvement of integration of the semiconductor device, a method has been introduced for forming the capacitor with a dielectric film having a high electric constant, forming the dielectric film to be thin, or increasing an area of the capacitor, so as to secure high capacitance in a small area.
In order to increase the area of the capacitor, many techniques are introduced such as a technique for forming a multilayer capacitor or a trench capacitor, or a technique for employing a semi spherical poly silicon film. Those techniques however have problems of making the structure of the capacitor, and, owing to the complicated fabrication process, increasing manufacturing cost and lowering yield.
The dielectric substance of SiO2/Si3N4 is commonly employed for the dielectric film of the capacitor, and according to an electrode substance used for the capacitor, Poly insulator poly (PIP) capacitor, or MIM capacitor is employed. Contrary to a junction capacitor, since a thin film type capacitor such as the PIP capacitor or the MIM capacitor is independent of bias, it is widely used in analog products demanding great precision.
In the case of a MIM capacitor, there is a disadvantage that it is difficult to make the capacitor with larger capacitance per unit area than the PIP capacitor. On the other hand, there is an advantage that, since the voltage coefficient for capacitor (Vcc) and temperature coefficient for capacitor (TCC) of the capacitance according to voltage or temperature are better than those of the PIP capacitor, it is easy to make the analog product with high precision.
Owing to an allergy reaction at an area conjunction with a lower layer, the method for etching an upper metal layer of a conventional capacitor as above described has a problem of causing an inferior formation of the upper metal layer and a metal pattern in the end. Moreover, the present inventor recognized that by etching the upper metal in one step, “notches” are formed at edges of the upper metal layer and lower nitride layer. Also, the inventor recognized that one step removal of the upper metal causes a polymer to form and an uneven SiN layer remains.